Heretofore, for image processing of video signals and the like an on-chip linear processor array or a media processor having SIMD (Single Instruction Multiple Data) instructions with a configuration similar to the linear processor array, has been used. For example, in a linear processor array directed to video image recognition processing, disclosed in Non-Patent Document 1, as shown in FIG. 7, an image is inputted in row units sequentially from one edge, and by allocating to adjacent PEs one to several adjacent image sequences, based on SIMD control, each PE implements parallel processing of only the number of PEs, by applying an instruction which has been broadcasted from a control processor (CP) to data in its own local memory.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-05-342184
[Non-Patent Document 1]
Kyo Shorin, et al., A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements, Technical Report of The Institute of Electronics, Information and Communications Engineers, Integrated Circuits and Devices Research Meeting (ICD), May 2003, Vol. 103, No. 89, pp. 19-24.